CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 72 of 153
6.5.5
144-bit Single Search for Cascade Up to 31 Devices
The hardware diagram of the Search subsystem of 31 devices is shown in Figure 6-19. Each of the four blocks in the diagram
represents eight Ayama 10000 devices (except the last, which has seven devices). The diagram for a block of eight devices is
very similar to the hardware diagram in Figure 6-9, except that the BHI[2:0] signals are connected to BHO of the previous block
(rather than being grounded) as shown in Figure 6-9. The following are the parameters programmed into the 31 devices:
• First thirty devices (devices 0–29): TLSZ = 10 (binary), HLAT = 001 (binary), LRAM = 0 (binary), and LDEV = 0 (binary).
• Thirty-first device (device 30): TLSZ = 10 (binary), HLAT = 001 (binary), LRAM = 1 (binary), and LDEV = 1 (binary).
• For Non-Enhanced Mode, CFG[63:0] = 5555555555555555 (hex) for all devices for CYNSE10512. CFG[31:0] = 55555555
(hex) for all devices for CYNSE10256, and CFG[15:0] = 5555 (hex) for all devices for CYNSE10128. For Enhanced Mode,
NES in each block for all devices should be set to “01” to create 144-bit table.
• The device receiving all the LHO signals from the other devices is considered the last device.
• All the shared signals showing tri-stated condition (“z”) indicate that, that particular device is not driving the shared signals.
The shared signals are not three-stated in a real life because other devices will be driving them.
• Comparing the hardware diagrams shown in Figure 6-9 and Figure 6-14, enabling MultiSearch does not mean that a board
layout change is required. The LHO_1_L and LHI_1_L share the same pin with the Full In and Full Out signals, which are not
shown in Figure 6-9. Cascading multiple devices together still allow the user to configure the devices through software to
perform single-search or MultiSearch operations without any board change.
The timing diagrams referred to in this paragraph reference the Hit/Miss assumptions defined in Table 6-8. For the purpose of
illustrating the timings, it is further assumed that there is only one device with a matching entry in each of the blocks. Figure 6-
20 shows the timing diagram for a Search command in the 144-bit-configured table of 31 devices for each of the eight devices
in block number 0. Figure 6-21 shows the same for the all the devices in block number 1 (above the winning device in that block).
Figure 6-22 shows the timing diagram for the globally winning device (defined as the final winner within its own and all blocks) in
block number 1. Figure 6-23 shows the timing diagram for all the devices below the globally winning device in block number 1.
Figure 6-24, Figure 6-25, and Figure 6-26 show the timing diagrams of the devices above the globally winning device, the globally
winning device, and the devices below the globally winning device, respectively, for block number 2. Figure 6-27, Figure 6-28,
Figure 6-29, and Figure 6-30 show the timing diagrams of the devices above globally winning device, the globally winning device,
and the devices below the globally winning device except the last device (device 30), respectively, for block number 3.
The 144-bit Search operation is pipelined and executes as follows:
• Four cycles from the Search command, each of the devices knows the outcome internal to it for that operation.
• On the fifth cycle, the devices arbitrate for a winner within a block (a “block” is defined as less than or equal to eight devices
resolving the winner within them using the LHI[6:0] and LHO[1:0] signalling mechanism).
• On the sixth cycle after the Search command, the blocks (of devices) resolve the winning block through the BHI[2:0] and
BHO[2:0] signalling mechanism. The winning device within the winning block is the global winning device for a Search operation.
Table 6-8. Hit/Miss Assumptions
Search Number
1
2
3
4
Block 0
MissMissMiss
Miss
Block 1
Miss
Miss
Hit
Miss
Block 2
Miss
Hit
Hit
Miss
Block 3
Hit
Hit
Miss
Miss
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