CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 71 of 153
The following is the sequence of operation for a single 72-bit MultiSearch command (also refer to Subsection 6.2, “Command
Bus Parameters,” on page 50).
• Cycle A:
— Command Bus: The host ASIC drives CMDV HIGH and applies Search command CMD[1:0] = “10”. The CMD[2] signal
must be driven to logic 0. {CMD[10], CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search
operation. CMD[7:6] signals must be driven with the same bits that will be driven on SADR[24:23] for CYNSE10512,
SADR[23:22] for CYNSE10256, SADR[22:21] for CYNSE10128 by this device if it has a hit. CMD[8] must be set to logic
1, and CMD[9] must be set to logic 0.
— DQ Bus: DQ[71:0] must be driven with the 72-bit data to be compared against the upper half (array 0) of the device entries.
• Cycle B:
— Command Bus: The host ASIC continues to drive CMDV HIGH and to apply Search command CMD[1:0] = “10”. CMD[5:2]
must be driven with the index of the Comparand Register. CMD[8:6] signals must be driven with the index of the SSR that
will be used for storing the address of the matching entry and the hit flag (see page 27 for information on SSR[0:7]).
CMD[10:9] are don’t cares during this cycle.
— DQ Bus: The DQ[71:0] is driven with the data that needs to compared with lower half (array 1) of the device entries.
The logical 72-bit Search operation is shown in Figure 6-18. The upper half of the device consisting of 72-bit entries is compared
to a 72-bit word that is presented on the DQ bus in cycles A using the GMR and local mask bits. The GMR used is the 72-bit word
specified in the even GMR selected by the GMR Index in the command’s cycle A. The lower half of the device consisting of 72-
bit entries is compared to a 72-bit word that is presented on the DQ bus in cycles B using the GMR and local mask bits. The GMR
used is the 72-bit word specified in the odd GMR selected by the GMR Index in the command’s cycle A. The result of the two
searches from the two halves are driven as two SRAM cycles as shown in the timing diagram. A matching entry from each array
that satisfies the Soft Priority and Mini-Key scheme will be the winning entries, and their location addresses La and Lb will be
driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 121), N = 25 for
CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128.
The Search command is a pipelined operation and executes a Search at the frequency of CLK2X for 72-bit searches in ×72-
configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 72-bit Search command cycle (two CLK2X
cycles) is shown in Table 6-4. Search latency from command to SRAM access cycle is 5 from a single device upto eight devices
in the table with TLSZ = 01. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 6-5.
71
0
Location
0
1
2
3
N/2 - 1
(72-bit configuration)
address
Data from Cycle A
GMR(even)
71
0
(First matching entry in
La
Figure 6-18. ×72 Table with in MultiSearchMode
71
0
Location
N/2
N/2 + 1
N/2 + 2
N/2 + 3
N-1
address
Data from Cycle B
GMR
71
0
(First matching entry in
Lb
the lower half)
the upper half)
Upper half (array 0)
Lower half (array 1)
N = 262144 for CYNSE10512
131072 for CYNSE10256
65536 for CYNSE10128
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