CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 70 of 153
• When more than one device is cascaded, the last device is always the default driver of the SRAM interface signals, i.e., when
none of the devices is driving, the last device will set the SRAM interface signals to a known default state. When other devices
are driving, the last device will set its I/Os on the SRAM interface to High-Z.
• Referring to Figure 6-17, the last device drives the SRAM interface signals until the end of cycle #5. From cycle #6 onwards,
its I/Os are three-stated to allow other devices to drive the SRAM interface signals, except when it’s its turn to drive. This goes
on until the end of cycle #10, and at the beginning of cycle #11, it drives the SRAM interface to a known default state again
when no other devices are driving.
cycle
CLK2X
CMDV
CMD[1:0]
DQ
CE_L
OE_L
Miss on
CMD[10:2]
M-Search2 M-Search4
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
HLAT = 001 (binary), TLSZ = 01 (binary), LRAM = 1 (binary), LDEV = 1 (binary).
Note: |(LHI_0[6:0]) and &(LHI_1_L[6:0]) stands for the boolean ‘OR’ and ‘AND’ respectively of the entire LHI bus.
Note: Each bit in LHO_0[1:0] and LHO_1_L[1:0] is the same logical signal.
PHS_L
SADR[M:0]
SSF
SSV
10
10
10
10
M-Search1 M-Search3
A B A B A B A B
0
Local
winner but
not global
winner
|(LHI_0[6:0])
LHO_0[1:0]
this device
0
z
0
ALE_L
WE_L
Global
winner
z
Figure 6-17. Timing Diagram for 72-bit MultiSearch Device Number 7 (Last Device)
A
C
E
G
F
DH
B
Addr
Addr
z
0
0
z
0
0
Miss on
this device
Local but not
global winner
Global
winner
&(LHI_1_L[6:0])
LHO_1_L[1:0]
10
M-Search5
A B
I J
0
01
1
z
0
0
0
0
1
0
1
1
1
1
1
0
0
1
1
1
1
z
z
z
0
z
1
0
z
1
z
0
0
1
z
z
z
z
z
0
0
0
“Gray Area”
= the last device
is driving the bus
to a known state.
D
G
M = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128
0
z
1
0
z
1
z
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