CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 7 of 153
LIST OF FIGURES (continued)
Figure 6-59. Timing Diagram of 576-bit Learn from CMPR Register (One Device) ............................ 117
Figure 6-60. Timing Diagram of Learn (TLSZ = 00 (binary), LDEV = 1 (binary)) ................................... 118
Figure 6-61. Timing Diagram of Learn (Except on the Last Device [TLSZ = 01 (binary)])................... 119
Figure 6-62. Timing Diagram of Learn on Device Number 7 (TLSZ = 01 (binary)).............................. 120
Figure 6-63. SRAM Read Access (TLSZ = 00 (binary), HLAT = 000 (binary),
LRAM = 1 (binary), LDEV = 1 (binary))................................................................................................ 122
Figure 6-64. Hardware Diagram of a Block of Eight Devices .............................................................. 123
Figure 6-65. SRAM Read of Device #0 in a Block of Eight Devices.................................................... 124
Figure 6-66. SRAM Read Timing of Device #7 in a Block of Eight Devices ........................................ 125
Figure 6-67. Hardware Diagram of 31 Devices Using Four Blocks ..................................................... 126
Figure 6-68. SRAM Read of Device #0 in a Bank of 31 Devices......................................................... 126
Figure 6-69. SRAM Read of Device #0 in a Bank of 31 Devices......................................................... 127
Figure 6-70. SRAM Write Access (TLSZ = 00 (binary), HLAT = 000 (binary),
LRAM = 1 (binary), LDEV = 1 (binary))................................................................................................ 128
Figure 6-71. Hardware Diagram of a Block of Eight Devices .............................................................. 129
Figure 6-72. SRAM Write of Device #0 in a Block of Eight Devices .................................................... 130
Figure 6-73. SRAM Write Timing of Device #7 in Block of Eight Devices ........................................... 131
Figure 6-74. Table of 31 Devices (Four Blocks) ..................................................................................132
Figure 6-75. SRAM Write of Device #0 in Bank of 31 Devices............................................................ 132
Figure 6-76. SRAM Write Through Device #30 in Bank of 31 Devices ............................................... 133
Figure 6-77. Timing Diagram for Full Signal (TLSZ = 10).................................................................... 134
Figure 8-1. Typical Power Consumption of Ayama 10000 .................................................................. 136
Figure 10-1. AC Timing Wave Forms with CLK2X .............................................................................. 139
Figure 10-2. AC Timing Wave Forms with CLK1X .............................................................................. 142
Figure 10-3. LVCMOS I/O Input Waveform ......................................................................................... 143
Figure 10-4. Test Condition of 2.5V LVCMOS I/O Output Load Equivalent ........................................ 143
Figure 10-5. Test Condition of 2.5V High-Z LVCMOS I/O Output Load Equivalent ........................... 143
Figure 10-6. Test Condition of 1.8V High-Z LVCMOS I/O Output Load Equivalent ............................ 143
Figure 10-7. HSTL I/II I/O Input Waveform .......................................................................................... 144
Figure 10-8. Test Condition of HSTL I I/O Output Load Equivalent..................................................... 144
Figure 10-9. Test Condition of HSTL II I/O Output Load Equivalent.................................................... 144
Figure 10-10. Test Condition of HSTLI/II I/O High-Z Output Load Equivalent..................................... 144
Figure 11-1. Pinout Diagram (Top View) ............................................................................................. 145
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