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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 69 of 153
cycle
CLK2X
CMDV
CMD[1:0]
DQ
CE_L
OE_L
CMD[10:2]
M-Search2 M-Search4
WE_L
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
HLAT = 001 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary).
Note: |(LHI_0[6:0]) and &(LHI_1_L[6:0]) stands for the boolean ‘OR’ and ‘AND’ respectively of the entire LHI bus.
Note: Each bit in LHO_0[1:0] and LHO_1_L[1:0] is the same logical signal.
PHS_L
SADR[M:0]
SSF
SSV
ALE_L
10
10
10
10
M-Search1 M-Search3
A B A B A B A B
Addr
z
z
z
z
z
0
0
|(LHI_0[6:0])
LHO_0[1:0]
Figure 6-16. Timing Diagram for 72-bit MultiSearch Device Number 1
Addr
z
Hit - this
Miss
Local hit
Miss
Hit
Miss Miss
z
z
0
0
z
z
z
1
1
z
1
1
z
z
device is
global
winner
but not
global
winner
&(LHI_1_L[6:0])
LHO_1_L[1:0]
1
0
1
0
0
0
1
1
0
1
0
1
z
z
10
M-Search5
A B
0
1
1
0
0
1
0
A
C
E
G
F
DH
B
I J
B
F
M = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128
Miss
1
1
z
z
z
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