CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 68 of 153
Notes:
• Each “cycle” consists of 2 CLK2x cycles, which is effectively one CLK1x cycle.
• The latency of SSV and SSF specified by HLAT refers to CLK1x cycles.
• LHO_0[1:0] will be valid 4 (CLK1x) cycles after the search parameter is sampled, regardless of the number of searches entered;
e.g., the search parameter A entered on DQ bus is sampled at cycle 1, LHO_0[1:0] will be available at cycle 5.
• For TLSZ[1:0] = 01, all signals on SRAM interface will be driven 5 (CLK1x) cycles after the search parameter is sampled,
regardless of the number of searches; e.g., the search parameter A sampled on cycle 1 is a hit, thus the address value sent
to SADR bus and the rest of the SRAM control signals will be driven at cycle 6.
M-Search2 M-Search4
10
10
10
10
A B A B A B A B
10
A B
cycle
CLK2X
CMDV
CMD[1:0]
DQ
CE_L
OE_L
CMD[10:2]
WE_L
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
HLAT = 001 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary).
Note: |(LHI_0[6:0]) and &(LHI_1_L[6:0]) stands for the boolean ‘OR’ and ‘AND’ respectively of the entire LHI bus.
Note: Each bit in LHO_0[1:0] and LHO_1_L[1:0] is the same logical signal.
This timing diagram is for device #0 only, High-Z means this device is not driving, but other device in the cascade may be
driving the bus.
PHS_L
SADR[M:0]
SSF
SSV
ALE_L
M-Search1 M-Search3
z
z
z
z
0
0
|(LHI_0[6:0])
0
LHO_0[1:0]
Figure 6-15. Timing Diagram for 72-bit MultiSearch Device Number 0
0
0
z
z
z
z
z
0
0
0
0
z
z
z
z
z
1
1
1
1
z
z
z
z
z
1
1
1
1
z
z
Hit
Miss
Hit
Miss Hit
Miss
Hit
&(LHI_1_L[6:0])
1
LHO_1_L[1:0]
0
1
1
0
0
1
M-Search5
cycle
11
cycle
12
0
0
1
1
0
A
C
E
G
F
DH
B
I J
Addr Addr
z
z
Addr
Addr
z
z
z
Addr
Addr
A
C
E
H
I
J
M = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128
z
z
z
1
1
1
1
z
z
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