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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 66 of 153
Notes:
• In MultiSearchMode, there is a separate set of the LHO and LHI signals corresponding to memory array 0 and array 1.
LHO_0[1:0] and LHI_0[6:0] corresponds to array 0 whereas LHO_1_L[1:0] and LHI_1_L[6:0] corresponds to array 1. The latter
share the same pins as FULO[1:0] and FULI[6:0] respectively.
• Both LHO_0[1] and LHO_0[0] are exact same signals so that the loads can be shared by two outputs. The same is true for
LHO_1_L[1] and LHO_1_L[0].
• Unused LHI_0 signals should be tied to ground whereas unused LHI_1_L signals should be tied to VDDQ_ASIC, which is either
1.8V or 2.5V only.
LHO_0[0]
6 5 43 21 0
LHI_0
LHO_0[0]
LHI_0
LHO_0[1]
LHI_0
LHO_0[0]
LHI_0
LHO_0[0]
LHI_0
LHO_0[0]
LHO_0[0]
BHO[0]
LHI_0
LHO[0]
LHI_0
LHI_0
LHO_0[1]
LHO_0[1]
LHO_0[1]
BHO[1]
BHO[0]
BHO[1]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
DQ[71:0]
SRAM
LHO_0[1] LHO_0[0]
Ayama 10000 #0
Ayama 10000 #1
Ayama 10000 #2
Ayama 10000 #3
Ayama 10000 #4
Ayama 10000 #5
Ayama 10000 #7
BHO[2] BHO[2]
CMDV
CMD[10:0]
SSF, SSV
Ayama 10000 #6
6 5 43 21 0
6 5 43 21 0
6 5 43 21 0
6 5 43 21 0
6 5 43 21 0
6 5 43 21 0
6 5 43 21 0
LHO_1_L[0]
6 5 43 21 0
LHI_1_L
LHO_1_L[0]
LHI_1_L
LHO_1_L[1]
LHI_1_L
LHO_1_L[0]
LHI_1_L
LHO_1_L[0]
LHI_1_L
LHO_1_L[0]
LHO_1_L[0]
LHI_1_L
LHO_1_L[0]
LHI_1_L
LHI_1_L
LHO_1_L[1]
LHO_1_L[1]
LHO_1_L[1]
6 5 43 21 0
6 5 43 21 0
6 5 43 21 0
6 5 43 21 0
6 5 43 21 0
6 5 43 21 0
6 5 43 21 0
LHO_1_L[1] LHO_1_L[0]
Figure 6-14. Hardware Diagram for a Table with Eight Devices for MultiSearch
VDDQ_ASIC
VDDQ_ASIC
VDDQ_ASIC
VDDQ_ASIC
VDDQ_ASIC
VDDQ_ASIC
VDDQ_ASIC
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