CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 65 of 153
The logical 72-bit Search operation is shown in Figure 6-13. The entire table of 72-bit entries (eight devices) is compared to a
72-bit word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and local mask bits. The effective
GMR is the 72-bit word specified by the identical value in both even and odd GMR pairs, in each of the eight devices, and selected
by the GMR Index in the command’s cycle A. The 72-bit word K (presented on the DQ bus in both cycles A and B of the command)
is also stored in both even and odd comparand register pairs (selected by the comparand register index in command cycle B) in
each of the eight devices. In the ×72 configuration, only the even comparand register can subsequently be used by the Learn
command in one of the devices (the first non-full device only). The word K (presented on the DQ bus in both cycles A and B of
the command) is compared with each entry in the table, starting at location 0. A matching entry that satisfies the Soft Priority and
Mini-Key scheme (for Enhanced Mode) will be the winning entry, and its location address L will be driven as part of the SRAM
address on the SADR[N:0] lines (see Section 6.7, “SRAM PIO Access,” on page 121), N = 25 for CYNSE10512, 24 for
CYNSE10256, 23 for CYNSE10128. The global winning device will drive the bus in a specific cycle. On a global miss cycle, the
device with LRAM = 1 (default driving device for the SRAM bus) and LDEV = 1 (default driving device for SSF and SSV signals)
will be the default driver for such missed cycles.
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 72-bit
searches in ×72-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 72-bit Search command
cycle (two CLK2X cycles) is shown in Table 6-4.
The latency of the Search from command to SRAM access cycle is 5 for up to eight devices in the table (TLSZ = 01). SSV and
SSF also shift further to the right for different values of HLAT, as specified in Table 6-5.
6.5.4
72-bit MultiSearch for One Device or Cascade Up to Eight Devices
The multiple search operates the search commands in parallel on the upper half (array 0) and lower half (array 1) of the data
array in the device. The results from the two parallel searches are then driven on the SRAM bus at twice that rate relative to
single-search. The hardware diagram of the Search subsystem of up to eight devices is shown in Figure 6-14 below.
Note:
• MultiSearch feature is only available in the Enhanced Mode, not in the Non-Enhanced Mode.
• Comparing the hardware diagrams shown in Figure 6-9 and Figure 6-14, enabling MultiSearch does not mean that a board
layout change is required. The LHO_1_L and LHI_1_L share the same pin with the Full In and Full Out signals, which are not
shown in Figure 6-9. Cascading multiple devices together still allow the user to configure the devices through software to
perform single-search or MultiSearch operations without any board change.
• The device receiving all the LHO signals from the other devices is the last device.
• All the shared signals showing three-stated condition (“z”) indicate that, that particular device is not driving the shared signals.
The shared signals are not three-stated in a real life because other devices will be driving them.
71
0
Location
0
1
2
3
N
(72-bit configuration)
address
K
GMR
Comparand Register (Odd)
Comparand Register (Even)
K
K
71
0
71
0
(First matching entry)
L
Must be same in each of the eight
devices
Will be same in each of the eight
devices
Figure 6-13. ×72 Table with Eight Devices
N = 2097151 for CYNSE10512
1048575 for CYNSE10256
524287 for CYNSE10128
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