63 / 153 page
CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 63 of 153
CFG[N:0] are all zeroes for Non-Enhanced Mode, N = 63 for CYNSE10512,
31 for CYNSE10256, 15 for CYNSE10128.
NES = 00 (binary) in each block for Enhanced Mode.
HLAT = 010 (binary), TLSZ = 01 (binary), LRAM = 0 (binary), LDEV = 0 (binary).
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
Search2
Search4
W
X
Y
Z
10
10
10
10
A B A B A B A B
cycle
CLK2X
CMDV
CMD[1:0]
DQ
CE_L
OE_L
(Miss
CMD[10:2]
WE_L
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
PHS_L
SADR[M:0]
SSF
SSV
ALE_L
Search1
Search2
Search3
Search4
Search1
Search3
Addr
z
z
z
1
z
(Local
winner
but not
global
winner)
(Miss
on this
device)
|(LHI[6:0])
LHO[1:0]
z
0
z
z
0
z
z
1
z
on this
device)
(This device
winner)
is global
Figure 6-11. Timing Diagram for 72-bit Search Device Number 1
0
0
0
0
0
1
1
1
X
M = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128
z
1
z
[+] Feedback
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
