CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 54 of 153
Write is a blocking operation and must be completed before the next operation can be issued.
6.4.1
Single Write
A single Write operation lasts 3 cycles (CLK1X) as illustrated in Figure 6-3.
Write operation sequence:
• Cycle 1A: The host ASIC applies the Write instruction to CMD[1:0] (CMD[2] = 0) using CMDV = 1, and the target address
supplied on the DQ bus. The host ASIC also supplies the GMR index to mask the Write to the data or mask array location on
{CMD[10], CMD[5:3]}. For SRAM WRITEs, the host ASIC must supply the SADR[25:23] for CYNSE10512, SADR[24:22] for
CYNSE10256, SADR[23:21] for CYNSE10128 on CMD[8:6]. The host ASIC sets CMD[9] to 0 for a normal Write.
• Cycle 1B:The host ASIC continues to apply the Write instruction to CMD[1:0] (CMD[2] = 0) using CMDV = 1, and the address
supplied on the DQ bus. The host ASIC continues to supply the GMR index to mask the Write to the data or mask array
locations in {CMD[10], CMD[5:3]}. The host ASIC selects the device where ID[4:0] matches the DQ[25:21] lines, or it selects
all the devices when DQ[25:21] = 11111.
• Cycle 2: The host ASIC drives DQ[71:0] with the data to be written to the data array, mask array, or register location of the
selected device.
• Cycle 3: Idle cycle. DQ bus should be driven to 0.
At the termination of cycle 3, another operation can begin.
6.4.2
Burst Write
The burst Write operation lasts 2 + n CLK1X cycles, where n is the number of the burst length as specified by the BLEN field of
the WBURREG. The BLEN field is automatically decremented after each Write of the burst, so the register must be re-initialized
before another burst Write is issued. Instead of the address provided by the user, the address in the INDEX field of the WBURREG
is used and incremented each cycle.
Table 6-3. Single/Burst Write Command Parameters
CMD Parameter
CMD[2]
Write Command
Description
0
Single Write
Writes a single location of the data array, mask array, NSE-associated SRAM or internal
registers. All access information is applied on the DQ bus.
1
Burst Write
Writes a block of locations to the data or mask array as a burst. WBURREG specifies the
starting address and the length of the data transfer from the data or mask array; it also
auto-increments the address for each access. All other access information is applied on
the DQ bus.
cycle 2
cycle 3
Write
Address
Data
CMDV
CMD[1:0]
DQ
0
cycle 1
cycle 0
cycle 4
CMD[10:2]
B
PHS_L
A
CLK2X
Figure 6-3. Single Write Cycle Timing
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