CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 52 of 153
6.3.1
Single Read
A single Read operation lasts six cycles (CLK1X) with the data driven out by the NSE on cycle 5 as illustrated in Figure 6-1.
Read operation sequence:
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 0) using CMDV = 1, and the DQ bus supplies
the address. The host ASIC selects the Ayama 10000 device for which ID[4:0] matches the DQ[25:21] lines. If DQ[25:21] =
11111, the host ASIC selects the Ayama 10000 with the LDEV bit set. The host ASIC also supplies SADR[25:23] for
CYNSE10512, SADR[24:22] for CYNSE10256, SADR[23:21] for CYNSE10128 on CMD[8:6] in cycle A of the Read instruction
if the Read is directed to the external SRAM.
• Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition.
• Cycle 4: The selected device starts to drive the DQ[71:0] bus and drives the ACK signal from Z to LOW.
• Cycle 5: The selected device drives the Read data from the addressed location on the DQ[71:0] bus, and drives the ACK
signal HIGH.
• Cycle 6: The selected device floats the DQ[71:0] to a three-state condition and drives the ACK signal LOW.
At the termination of cycle 6, the selected device releases the ACK line to a three-state condition. The Read instruction is complete
and the next operation can begin.
6.3.2
Burst Read
The burst Read operation lasts 4 + 2n CLK1X cycles, where n is the number of the burst length as specified by the BLEN field
of the RBURREG. The BLEN field is automatically decremented after each Read of the burst, so the register must be reinitialized
before another burst Read is issued. Instead of the address provided by the user, the address in the INDEX field of the RBURREG
is used and incremented each cycle.
Figure 6-2 illustrates the timing diagram for the burst Read of the data or mask array.
cycle
cycle
cycle
cycle
cycle
cycle
Read
Address
0Data
1
2
345
6
CLK2X
CMDV
CMD[1:0]
ACK
DQ
CMD[10:2]
A
B
PHS_L
Figure 6-1. Single-Location Read Cycle Timing
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