CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 5 of 153
LIST OF FIGURES
Figure 2-1. Ayama™ 10000 Block Diagram ..........................................................................................11
Figure 2-2. Example of Switch/Router Implementation Using Ayama 10000 ........................................ 12
Figure 3-1. Ayama 10000 Database Table Widths................................................................................ 13
Figure 3-2. Multi-Width Database Configuration Example..................................................................... 13
Figure 3-3. Addressing the Ayama 10000 Data and Mask Arrays......................................................... 14
Figure 5-1. Blocks and Block Registers Association ............................................................................. 19
Figure 5-2. Mini-Key Register Contents................................................................................................. 19
Figure 5-3. Sub-Blocks and Soft Priority Associations .......................................................................... 20
Figure 5-4. Timing Diagram of a DQ Bus Parity Error (288-bit Search, TLSZ=00)................................ 21
Figure 5-5. Timing Diagram of a Core Parity Error (TLSZ=00).............................................................. 22
Figure 5-6. MultiSearch Operation Overview......................................................................................... 22
Figure 5-7. Ayama 10000 I/O Interfaces................................................................................................ 24
Figure 5-8. Comparand Register Selection During Search and Learn Instructions............................... 26
Figure 5-9. Addressing the Global Mask Register Array ....................................................................... 27
Figure 5-10. Search Successful Register .............................................................................................. 27
Figure 5-11. Command Register ........................................................................................................... 28
Figure 5-12. Information Register .......................................................................................................... 30
Figure 5-13. Read Burst Register .......................................................................................................... 30
Figure 5-14. Write Burst Address Register ............................................................................................ 31
Figure 5-15. Next-free Address Register ............................................................................................... 31
Figure 5-16. Configuration Register....................................................................................................... 32
Figure 5-17. Hardware Register ............................................................................................................ 33
Figure 5-18. Parity Control Register ...................................................................................................... 34
Figure 5-19. Selection of the CPR through GMR Index......................................................................... 35
Figure 5-20. Control Register ................................................................................................................ 35
Figure 5-21. Search Result Register ..................................................................................................... 36
Figure 5-22. Block Mini-Key Register .................................................................................................... 37
Figure 5-23. Block Priority Register ....................................................................................................... 38
Figure 5-24. Block Parity Register ......................................................................................................... 39
Figure 5-25. Block NFA Register ........................................................................................................... 39
Figure 5-26. Block Priority Register Aliases .......................................................................................... 40
Figure 5-27. Ayama 10000 Clocks (CLK2X and PHS_L) ...................................................................... 42
Figure 5-28. Ayama 10000 Clocks (CLK1X).......................................................................................... 42
Figure 5-29. Ayama 10000 Clocks for All Timing Diagrams .................................................................. 42
Figure 5-30. Data Array, Mask Array and External SRAM Address Space Encoding ........................... 44
Figure 5-31. Internal Register Address Space Encoding....................................................................... 45
Figure 5-32. Depth Cascading in a Single Block ................................................................................... 46
Figure 5-33. Depth Cascading 4 Blocks ................................................................................................ 47
Figure 5-34. FULL Signal Generation in a Cascaded Table.................................................................. 48
Figure 5-35. Proper Power-up Sequence .............................................................................................. 49
Figure 6-1. Single-Location Read Cycle Timing .................................................................................... 52
Figure 6-2. Burst Read of the Data and Mask Arrays (BLEN = 4) ......................................................... 53
Figure 6-3. Single Write Cycle Timing ................................................................................................... 54
Figure 6-4. Burst Write of the Data and Mask Arrays (BLEN = 4) ......................................................... 55
Figure 6-5. Timing Diagram for Mixed Single Search (One Device)...................................................... 57
Figure 6-6. Multiwidth Configurations Using CYNSE10512 as an Example.......................................... 58
Figure 6-7. Timing Diagram for Mixed MultiSearch (One Device) ......................................................... 59
Figure 6-8. Multiwidth Configurations Using CYNSE10512 as an Example.......................................... 60
Figure 6-9. Hardware Diagram for a Table with Eight Devices.............................................................. 61
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