CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 49 of 153
On an Indirect Write operation, if the CHIPID field matches the current device, this device will perform the write request. If the
CHIPID field does not match, the device will not respond. If the CHIPID is set to broadcast, different actions occur based upon
the target. If the target is an internal register, the write request is ignored. If the target is a Data or Mask array, the device with the
VAL field of the SSR register set performs the write request. If the target is external SRAM, the device with the LRAM field set
will drive the SRAM signals.
5.12
Power-up Sequence
Ayama 10000 requires that the power supplies follow a known sequence to ensure successful device power-up to set the device
to its initial state. RST_L should be held Low before the power supplies ramp-up and must be held Low for a duration of time
afterward. Clock signals (CLK1X/CLK2X and PHS_L) should start running after the power supplies become stable. All IO voltages
(VDDQ, which includes VDDQ_ASIC and VDDQ_SRAM) should only ramp up only after the core voltage (VDD) level reaches 90% point.
The following describes the proper power-up sequence required to correctly initialize the Cypress Network Search Engines before
functional access to the device can begin. The following steps are presented in order of priority.
1. Hold RST_L and TRST_L signals low and power up VDD. Then power up VDDQ when VDD is stable. TRST_L can be tied to
RST_L, tied low permanently, or driven asynchronously (more information on resetting JTAG in the JTAG section of the
datasheet).
2. Start running CLK2X/CLK1X and PHS_L (if applicable) after VDDQ powers up.
3. Hold RST_L low for at least 0.5 ms + tRSTL after the clock signal is stable, then drive high.
RST_L should be set High with sufficient hold time with respect to CLK2X. Following steps 1 through 3 will power up the device
gracefully and ensure proper operation of the device. Figure 5-35 illustrates the proper sequences of the power-up operation.
Note: The PLL will lose lock if the CLK2X/CLK1X or PHS_L (if applicable) stop transitioning.
Figure 5-35. Proper Power-up Sequence
VDD
VDDQ
PLL lock time, 0.5 ms
tRSTL
CLK2X
PHS_L
TRST_L/RST_L
TRST_L
asynchronous delay
TRST_L
TRST_L can either be
driven asynchronously,
tied Low permanently, or
tied to RST_L
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