CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 43 of 153
5.7
Phase-Locked Loop
When the device first powers up, it takes 0.5 milliseconds (ms) after the power supplies are stable to lock the internal PLL. During
this time period, the RST_L must be held LOW for proper power-up. All signals to the device in CLK1X mode are sampled by a
clock that is generated by multiplying CLK1X by two. Since the PLL has a locking range, the device will only work between the
range of frequencies specified in the timing specification wave form section of this data sheet (see Section 10.0, “AC Timing
Parameters, Waveforms and Test Conditions,” on page 138).
5.8
Pipeline Latency
Pipeline latency is used to give enough time for a cascaded system’s arbitration logic to determine the device that will drive the
output of an operation on the SRAM bus. The Ayama 10000 has a default of 4 CLK1X pipeline latencies but more latency can
be added as necessary. The number of additional pipeline stages is set in the TLSZ and HLAT fields of the COMMAND Register.
The number of pipeline stages also controls the maximum operating speed for a single Ayama 10000 NSE. Table 5-24 lists the
additional pipeline stages and the maximum operating speed.
Table 5-24. Pipeline Stages and Maximum Operating Speed.
Internal register for configuration: CMD
5.9
DQ Bus Encoding of Ayama 10000 Address Space
A set of parameters for an operation must be provided in the DQ bus to the NSE along with the command sent in the CMD bus.
This section covers the encoding of the parameters expected in the DQ bus. There are two ways of addressing an entry location
or an internal register within the device: Direct and Indirect. The internal registers can only use Direct addressing while Data array,
Mask array and SRAM access operations can use either Direct or Indirect. Indirect addressing allows the use of the SSR register
INDEX field as the address for a Read, Write and Learn operations. Indirect Read operation on the internal registers will return
undefined values.
TLSZ
Additional CLK1X Cycle Latency
Total Search CLK1X Cycle Latency
Maximum Operating Speed
(CLK1X/CLK2X)
00
0
4
83/166 MHz
01
1
5
100/200 MHz
10
2
6
133/266 MHz
11
Invalid
Invalid
Invalid
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