CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 42 of 153
5.6
Clocks
If the CLK_MODE pin is LOW, Ayama 10000 receives the CLK2X and PHS_L signals. It uses the PHS_L signal to divide CLK2X
and generate an internal clock (CLK[6]), as shown in Figure 5-27. If the CLK_MODE pin is HIGH, Ayama 10000 receives CLK1X
only. Ayama 10000 uses an internal phase-locked loop (PLL) to lock the frequency of CLK1X and generates the internal clock
CLK, as shown in Figure 5-28. Also noted on these figures are cycles A and B. In CLK2X mode, cycle A begins on the rising edge
of CLK2X, when PHS_L is Low, and ends on the next rising edge. Cycle B begins on the rising edge of CLK2X when PHS_L is
High, and ends on the subsequent CLK2X rising edge. For CLK1X mode, the falling edge of CLK1X is considered the end of
cycle A, while the rising edge after that is considered the end of cycle B. Valid data must be available for the NSE at the END of
any cycle. Note. For the purpose of showing timing diagrams, all such diagrams in this document will be shown in CLK2X mode.
For a timing diagram in CLK1X mode, the following substitution can be made (see Figure 5-29).
Notes:
6.
“CLK” is an internal clock signal.
7.
Any reference to “CLK” cycles means one cycle of CLK.
8.
Only supported in Non-Enhanced mode.
CLK2X
PHS_L
CLK[7]
Figure 5-27. Ayama 10000 Clocks (CLK2X and PHS_L)
“Cycle A End”
“Cycle B End”
A
B
Input Data
CLK1X
CLK[7]
Figure 5-28. Ayama 10000 Clocks (CLK1X)
“Cycle A End” “Cycle B End”
AB
Input Data
CLK2X
PHS_L
CLK1X
Use for CLK2X mode
Use for CLK1X mode
Figure 5-29. Ayama 10000 Clocks for All Timing Diagrams
[+] Feedback
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
