CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 34 of 153
5.4.11
Parity Control Register (PARITY)
Table 5-12 describes the Parity Control Register fields. This register is only active when the device is in the Enhanced mode.
Table 5-12. Parity Control Register Description
Field
Range
(decimal)
Initial Value
(binary)
Description
INDEX
[18, N:0]
0
Index. This field contains the highest priority parity error index. When a parity error is
detected, the global priority encoder selects the highest priority parity error out of the entire
Core.
Note that if another Parity operation is performed, this field is updated based upon that
operation.
N = 17 for CYNSE10512, 16 for CYNSE10256 (bit [17] is reserved), 15 for CYNSE10128
(bits [17:16] are reserved). Bit[18] is used to indicate whether a mask (=1) or data (=0) entry
contained the error.
[27:19]
Reserved.
BMULTI
[28]
0
Multi DQ Parity Error Status Bit. This field is set to 1 when multiple errors were detected
during a bus transfer. It is also set to 1 when new parity error occurs and BERR is set. This
bit can only be cleared by a user Write.
BERR
[29]
0
DQ Parity Error Status Bit. This bit is set when a parity error is detected during a data
transfer across the DQ bus. This bit can only be cleared by a user Write.
MULTI
[30]
0
Multi-Parity Error Status Bit. This bit is set when more than one parity error in the Core is
detected during the Parity operation. It also updates when a new parity error occurs and ERR
is set. This bit can only be cleared by a user Write.
ERR
[31]
0
Parity Error Status Bit. This bit is set when any parity error in the Core is detected during
the Parity operation. This bit can only be cleared by a user Write.
ADR
[50, M:32]
0
Current Address. After a parity check, the address in this field is incremented and is ready
for the next address to check for parity. When the Parity operation finishes and an error is
detected, assuming no intervening new Parity operations, this field will point to the next entry
address to be checked. Bit[50] selects between mask (=1) or data (=0) array. As the address
is incremented, this bit is treated as the LSB and toggles before Bit[34]. Bit[33:32] are always
0 because Read Parity operation checks 4 adjacent 72-bit entries. M = 49 for CYNSE10512,
48 for CYNSE10256 (bit [49] is reserved), 47 for CYNSE10128 (bits [49:48] are reserved).
[71:51]
Reserved.
7
15
23
0
39
47
55
31
63
71
INDEX
ADR
Figure 5-18. Parity Control Register
N = 15 for CYNSE10128
N = 16 for CYNSE10256
N = 17 for CYNSE10512
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