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WM8941 Datasheet(PDF) 85 Page - Wolfson Microelectronics plc |
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WM8941 Datasheet(HTML) 85 Page - Wolfson Microelectronics plc |
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85 / 96 page  Pre Production WM8941 w PP, Rev 3.3, December 2007 85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 3:0 PLLN[3:0] 1100 Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Master Clock and Phase Locked Loop (PLL) 15:6 000h Reserved 37 (25h) 5:0 PLLK[23:18] 001100 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 15:9 00h Reserved 38 (26h) 8:0 PLLK[17:9] 010010011 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 15:9 00h Reserved 39 (27h) 8:0 PLLK[8:0] 011101001 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 15:5 000h Reserved 4 QBOOST 0 Increases the filters Q. Video Buffer 3 VBGAIN 0 Video buffer gain 0 = 0dB (=6dB unloaded) 1 = +6dB (=12dB unloaded) Video Buffer 2 VBDISOFF 0 Disable Video Buffer DC Offset 0 = Video buffer drives down to 40mV above ground 1 = Video buffer drives to ground (not recommended) Video Buffer 1 VBPULLDWN 0 Video buffer pull down Video Buffer 40 (28h) 0 VBCLAMPEN 0 Video buffer clamp enable 0 = Disabled 1 = Enabled Video Buffer 41 (29h) 15:0 0000h Reserved 15:2 0 Reserved 1 ALCZC 0 (zero cross off) ALC uses zero cross detection circuit. 0 = Disabled (recommended) 1 = Enabled 42 (2Ah) 0 0 Reserved ALC Control 4 43 (2Bh) 15:0 0000h Reserved 15:9 00h Reserved 8 MBVSEL 0 Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.75 * AVDD Input Signal Path 7:4 0h Reserved 3 AUXMODE 0 Auxiliary Input Mode 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed) Input Signal Path 2 AUX2INPPGA 0 Select AUX amplifier output as input PGA signal source. 0=AUX not connected to input PGA 1=AUX connected to input PGA amplifier negative terminal. Input Signal Path 44 (2Ch) 1 MICN2INPPGA 1 Connect MICN to input PGA negative terminal. 0=MICN not connected to input PGA 1=MICN connected to input PGA amplifier negative terminal. Input Signal Path |
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