CY7C1444AV25 datasheet(21/26 Pages) CYPRESS

Part #	CY7C1444AV25

Description	36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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21 / 26 page

CY7C1444AV25

CY7C1445AV25

Document #: 38-05351 Rev. *E

Page 21 of 26

Read/Write Cycle Timing[23, 25, 26]

Notes:

25. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.

26. GW is HIGH.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

OE

ADSC

CE

tAH

tAS

A2

tCEH

tCES

Data Out (Q)

High-Z

ADV

Single WRITE

D(A3)

A4

A5

A6

D(A5)

D(A6)

Data In (D)

BURST READ

Back-to-Back READs

High-Z

Q(A2)

Q(A1)

Q(A4)

Q(A4+1)

Q(A4+2)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

A1

BWE, BWX

A3

DON’T CARE

UNDEFINED

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CY7C1444AV25 Datasheet(PDF) 21 Page - Cypress Semiconductor

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