CY7C1444AV25 datasheet(20/26 Pages) CYPRESS

Part #	CY7C1444AV25

Description	36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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20 / 26 page

CY7C1444AV25

CY7C1445AV25

Document #: 38-05351 Rev. *E

Page 20 of 26

Write Cycle Timing[23, 24]

Note:

24. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

OE

ADSC

CE

tAH

tAS

A1

tCEH

tCES

BWE,

BWX

ADV

BURST READ

BURST WRITE

D(A2)

D(A2 + 1)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

A2

A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

t

OEHZ

tADVH

tADVS

tWEH

tWES

t

DH

t

DS

GW

tWEH

tWES

Byte write signals are ignored for first cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE

UNDEFINED

D(A1)

High-Z

Data in (D)

Data Out (Q)

Similar Part No. - CY7C1444AV25

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Similar Description - CY7C1444AV25

Manufacturer	Part #	Datasheet	Description
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CY7C1444AV25 Datasheet(PDF) 20 Page - Cypress Semiconductor

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