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CY7C1444AV25 Datasheet(PDF) 16 Page - Cypress Semiconductor

Part # CY7C1444AV25
Description  36-Mbit (1M x 36/2M x 18) Pipelined DCD Sync SRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1444AV25 Datasheet(HTML) 16 Page - Cypress Semiconductor

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CY7C1444AV25
CY7C1445AV25
Document #: 38-05351 Rev. *E
Page 16 of 26
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
°C to +150°C
Ambient Temperature with
Power Applied............................................. –55
°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND ..... –0.5V to + VDD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................................... >200 mA
Operating Range
Range
Ambient
Temperature
VDD
VDDQ
Commercial
0°C to +70°C
2.5V + 5%
1.7V to VDD
Industrial
–40°C to +85°C
Electrical Characteristics Over the Operating Range[14, 15]
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
2.375
2.625
V
VDDQ
I/O Supply Voltage
for 2.5V I/O
2.375
2.625
V
for 1.8V I/O
1.7
1.9
V
VOH
Output HIGH Voltage
for 2.5V I/O, IOH = –1.0 mA
2.0
V
for 1.8V I/O, IOH = –100 µA1.6
V
VOL
Output LOW Voltage
for 2.5V I/O, IOL = 1.0 mA
0.4
V
for 1.8V I/O, IOL= 100 µA0.2
V
VIH
Input HIGH Voltage[14]
for 2.5V I/O
1.7
VDD + 0.3V V
for 1.8V I/O
1.26
VDD + 0.3V V
VIL
Input LOW Voltage[14]
for 2.5V I/O
–0.3
0.7
V
for 1.8V I/O
–0.3
0.36
V
IX
Input Leakage Current
except ZZ and MODE
GND
≤ V
I ≤ VDDQ
–5
5
µA
Input Current of MODE Input = VSS
–30
µA
Input = VDD
5
µA
Input Current of ZZ
Input = VSS
–5
µA
Input = VDD
30
µA
IOZ
Output Leakage Current GND
≤ V
I ≤ VDDQ, Output Disabled
–5
5
µA
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle, 250 MHz
435
mA
5-ns cycle, 200 MHz
385
mA
6-ns cycle, 167 MHz
335
mA
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
All speeds
185
mA
ISB2
Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max, Device Deselected, VIN
0.3V or VIN > VDDQ – 0.3V,
f = 0
All speeds
120
mA
ISB3
Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max, Device Deselected,
or VIN ≤ 0.3V or
VIN > VDDQ – 0.3V f = fMAX = 1/tCYC
All speeds
160
mA
ISB4
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All Speeds
135
mA
Notes:
14. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
15. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.


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