CY7C1444AV25
CY7C1445AV25
Document #: 38-05351 Rev. *E
Page 12 of 26
“extest output bus tri-state”, is latched into the preload register
during the “Update-DR” state in the TAP controller, it will
directly control the state of the output (Q-bus) pins, when the
EXTEST is entered as the current instruction. When HIGH, it
will enable the output buffers to drive the output bus. When
LOW, this bit will place the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Symbol
Parameter
Min.
Max.
Unit
Clock
tTCYC
TCK Clock Cycle Time
50
ns
tTF
TCK Clock Frequency
20
MHz
tTH
TCK Clock HIGH time
20
ns
tTL
TCK Clock LOW time
20
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
tCS
Capture Set-up to TCK Rise
5
ns
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Notes:
9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
t
TL
Test Clock
(TCK)
123456
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED