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W83781D Datasheet(PDF) 25 Page - Winbond |
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W83781D Datasheet(HTML) 25 Page - Winbond |
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25 / 54 page  W83781D/W83781G Publication Release Date: April 14, 2005 - 21 - Revision 2.0 7 6 5 4 3 2 1 0 IN4 -IN5 -IN6 FAN3 Case Open Reserved Reserved RST_OUT# Enable Bit 7: <7> = 1 in SMI# ask Register 2 enables the RST_OUT# in the Configuration Register. 13.8 IRQ Mask Register 1 ⎯Index 45h Bit 6-5: Reserved. This bit should be set to 0. Bit 4-0: The logical 1 disables the corresponding interrupt status bit for SMI# interrupt. 8.8 IRQ Mask Register 2 – Index 45h (Bank 0) Register Location: 45h Power on Default Value 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 V25INA V25INB V33IN V5IN VTHIN1 VTHIN23 FAN1 FAN2 Bit 7-0: The logical 1 disables the corresponding interrupt status bit for IRQ interrupt. 8.9 IRQ Mask Register 2 – Index 46h (Bank 0) Register Location: 46h Power on Default Value <7:0> = 01000000 binary Attribute: Read/Write Size: 8 bits |
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