 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
XC9101 Datasheet(PDF) 13 Page - Torex Semiconductor |
|
||||||||||||||||||||||||||||||
XC9101 Datasheet(HTML) 13 Page - Torex Semiconductor |
|
|
13 / 22 page  13/22 XC9101 Series ● Instruction on Pattern Layout ① In order to stablize VDD's voltage level, we recommend that a by-pass capacitor (CDD) be connected as close as possible to the VIN & VSS pins. ② In order to stablize the GND voltage level which can fluctuate as a result of switching, we suggest that C_CLK's, R_CLK's & C_GAIN's GND be separated from Power GND and connected as close as possible to the VSS pin (by-pass capacitor, CDD). Please use a multi layer board and check the wiring carefully. < XC9101D Series Pattern Layout Examples> 2 Layer Evaluation Board ■ NOTES ON USE (Continued) Power GND IC GND VDD Line Through Hole RFB1 RFB2 CFB CL C_GAIN R_CLK C_CLK CDD L N-MOS RSEN SD VIN CIN C_SS R_SS 1 2 3 4 Through Hole 5 6 7 8 R_CLK, C_CLK, C_GAIN, RFB2 GND 1 2 3 4 5 6 7 85 6 7 8 5 6 7 8 |
Similar Part No. - XC9101_1 |
|
Similar Description - XC9101_1 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
