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With regard to the XC9101D series, the output voltage is set by attaching externally divided resistors. The output voltage

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NOTES ON USE

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Application Notes

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1. The XC9101 series are designed for use with an output ceramic capacitor. If, however, the potential difference

between input and output is too large, a ceramic capacitor may fail to absorb the resulting high switching energy and

oscillation could occur on the output side. If the input-output potential difference is large, connect an electrolytic

capacitor in parallel to compensate for insufficient capacitance.

2. The EXT pin of the XC9101 series is designed to minimize the through current that occurs in the internal circuitry.

However, the gate drive of external PMOS has a low impedance for the sake of speed. Therefore, if the input voltage is

high and the bypass capacitor is attached away from the IC, the charge/discharge current to the external PMOS may

lead to unstable operations due to switching operation of the EXT pin.

As a solution to this problem, place the bypass capacitor as close to the IC as possible, so that voltage variations at the

of ohms between the EXT pin and PMOS gate. Remember that the insertion of a resistor slows down the switching

speed and may result in reduced efficiency.

between the EXT pin and the base of the NPN transistor in order to limit the base current without slowing the switching

4. Although the C_CLK connection capacitance range is from 150 ~ 220pF, the most suitable value for maximum stability is

around 180pF.

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OPERATIONAL EXPLANATION (Continued)

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Functional Settings (Continued)

FB pin

Rfb1

Rfb2

Verr amplifier

0.9V

Cfb

Output voltage

Verr

EXT pin

Rb

Cb