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IS-2981RH Datasheet(PDF) 3 Page - Renesas Technology Corp |
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IS-2981RH Datasheet(HTML) 3 Page - Renesas Technology Corp |
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3 / 4 page ![]() IS-2981RH, IS-2981EH FN4869 Rev 1.00 Page 3 of 4 Jun 24, 2013 Die Characteristics DIE DIMENSIONS: 2667 µm x 5131µm (105 mils x 202 mils) Thickness: 483 µm ±25.4µm (19 mils ±1 mil) INTERFACE MATERIALS Glassivation Type: Nitride (Si3N4) over Silox (SiO2) Nitride Thickness: 4.0k Å ± 1.0kÅ Silox Thickness: 12.0k Å ±4.0kÅ Metallization Top Metal 2: Ti/AlCu Thickness: 1.6 µm ± 0.02µm Metal 1: Ti/AlCu Thickness: 0.8 µm ± 0.01µm Substrate HVTDLM, Bonded Wafer, Dielectric Isolation Backside Finish Silicon ASSEMBLY RELATED INFORMATION Substrate Potential Must be tied to GND. ADDITIONAL INFORMATION Worst Case Current Density <1.0 x 105 A/cm2 Transistor Count 68 Metallization Mask Layout IS-2981RH, IS-2981EH 87 6 5 4 3 2 1 9 9 10 11 12 13 14 15 16 17 18 10 10A 9 9 NOTES: 4. Pad numbers correspond to package pin functions. 5. Bond to all four pad 9 locations for VCC current sharing purposes. 6. Bond to both pad 10 locations for GND current sharing purposes. 7. Pad 10A is not used in die applications. 8. Die backside must be connected to GND. |
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