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M4T28-BR12SH1 Datasheet(PDF) 14 Page - STMicroelectronics

Part # M4T28-BR12SH1
Description  3.3V, 256Kbit (32Kbit x 8) TIMEKEEPER짰 SRAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M4T28-BR12SH1 Datasheet(HTML) 14 Page - STMicroelectronics

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Clock operations
M48T35AV
14/28
Table 5.
Register map
Keys:
S = Sign bit
FT = Frequency test bit (must be set to '0' upon power for normal operation)
R = Read bit
W = Write bit
ST = Stop bit
0 = Must be set to '0'
CEB = Century enable bit
CB = Century bit
Note:
When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century
(dependent upon the initial value set).
When CEB is set to '0,' CB will not toggle. The WRITE Bit does not need to be set to write to
CEB.
3.4
Calibrating the clock
The M48T35AV is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator
frequency error at 25°C, which equates to about ±1.53 minutes per month. With the
calibration bits properly set, the accuracy of each M48T35AV improves to better than +1/–2
ppm at 25°C.
The oscillation rate of any crystal changes with temperature (see Figure 9 on page 16).
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T35AV design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 10 on page 16. The number of times pulses
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five calibration bits found in the Control Register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order bits (D4-D0) in the Control Register
7FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit
D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration.
Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per
minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a
Address
Data
Function/range
BCD format
D7
D6
D5
D4
D3
D2
D1
D0
7FFFh
10 Years
Year
Year
00-99
7FFEh
0
0
0
10 M.
Month
Month
01-12
7FFDh
0
0
10 Date
Date
Date
01-31
7FFCh
0
FT
CEB
CB
0
Day
Century/day
00-01/01-07
7FFBh
0
0
10 Hours
Hours
Hours
00-23
7FFAh
0
10 minutes
Minutes
Minutes
00-59
7FF9h
ST
10 seconds
Seconds
Seconds
00-59
7FF8h
W
R
S
Calibration
Control


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