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TMP86FS49BUG Datasheet(PDF) 10 Page - Toshiba Semiconductor

Part # TMP86FS49BUG
Description  8 Bit Microcontroller
Download  294 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP86FS49BUG Datasheet(HTML) 10 Page - Toshiba Semiconductor

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3.3.2.2 Using data transfer instructions
3.3.3 Interrupt return ........................................................................................................................................ 41
3.4 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.4.1 Address error detection .......................................................................................................................... 42
3.4.2 Debugging .............................................................................................................................................. 42
3.5 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.6 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.7 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4. Special Function Register (SFR)
4.1 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5. I/O Ports
5.1 Port P0 (P07 to P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.2 Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3 Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.4 Port P3 (P37 to P30) (Large Current Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.5 Port P4 (P47 to P40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.6 Port P5 (P54 to P50) (Large Current Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.7 Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.8 Port P7 (P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6. Watchdog Timer (WDT)
6.1 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.2 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.2.1 Malfunction Detection Methods Using the Watchdog Timer................................................................... 66
6.2.2 Watchdog Timer Enable ......................................................................................................................... 67
6.2.3 Watchdog Timer Disable ........................................................................................................................ 68
6.2.4 Watchdog Timer Interrupt (INTWDT)...................................................................................................... 68
6.2.5 Watchdog Timer Reset ........................................................................................................................... 69
6.3 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.1 Selection of Address Trap in Internal RAM (ATAS)................................................................................ 70
6.3.2 Selection of Operation at Address Trap (ATOUT) .................................................................................. 70
6.3.3 Address Trap Interrupt (INTATRAP)....................................................................................................... 70
6.3.4 Address Trap Reset................................................................................................................................ 71
7. Time Base Timer (TBT)
7.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.1.1 Configuration .......................................................................................................................................... 73
7.1.2 Control .................................................................................................................................................... 73
7.1.3 Function .................................................................................................................................................. 74
7.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.2.1 Configuration .......................................................................................................................................... 75
7.2.2 Control .................................................................................................................................................... 75


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