All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

●

●

●

●

●

●

●

●

●

●

●

●

●

●

●

○

○

○

○

●

●

○

○

●

●

●

●

●

●

http://www.DigitalCoreDesign.com

http://www.dcd.pl

1-, 1½-, or 2-stop bit generation

KEY FEATURES

Software compatible with 16450, 16550

and 16750 UARTs

Configuration capability

Separate configurable BAUD clock line

Two modes of operation: UART mode and

FIFO mode

Majority Voting Logic

In the FIFO mode transmitter and receiver

are each buffered with 16 byte or 64 byte

FIFO to reduce the number of interrupts

presented to the CPU

Optional FIFO size extension to 128, 256

or 512 Bytes

Adds or deletes standard asynchronous

communication bits (start, stop, and parity)

to or from the serial data

In UART mode receiver and transmitter

are double buffered to eliminate a need for

precise synchronization between the CPU

and serial data

Independently controlled transmit, receive,

line status, and data set interrupts

False start bit detection

16 bit programmable baud generator

MODEM control functions (CTS, RTS,

DSR, DTR, RI, and DCD)

Programmable automatic Hardware Flow

Control logic through Auto-RTS and Auto-

CTS

Fully

programmable

serial-interface

characteristics:

5-, 6-, 7-, or 8-bit characters

Even, odd, or no-parity bit generation and

detection

Baud generation

Complete status reporting capabilities

Line break generation and detection.

Internal diagnostic capabilities:

Loop-back controls for communications link

fault isolation

Break, parity, overrun, framing error

simulation

Two DMA Modes allows single and multi-

transfer

Technology independent HDL Source

Code

Full prioritized interrupt system controls

Fully synthesizable static design with no

internal tri-state buffers

APPLI C ATIONS

Serial Data communications applications

Modem interface

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design

license allows use IP Core in

single

FPGA

bitstream

and

ASIC

implementation.

Unlimited Designs, One Year

licenses allow

use IP Core in unlimited number of FPGA

bitstreams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time

restriction except One Year license where

time of use is limited to 12 months.

●

○

Single Design license for

VHDL, Verilog source code called HDL

Source

○

Encrypted, or plain text EDIF called Netlist

●

○

●

○

○

●

○

○

One Year license for

Encrypted Netlist only

Unlimited Designs license for

HDL Source

Netlist

Upgrade from

HDL Source to Netlist

Single Design to Unlimited Designs