sn74v3640 datasheet(24/50 Pages) TI

Part #	SN74V3640

Description	1024 횞 36, 2048 횞 36, 4096 횞 36, 8192 횞 36, 16384 횞 36, 32768 횞 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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24 / 50 page

SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690

1024

× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003

24

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

parallel programming mode (continued)

See Figures 3 and 17 for timing information.

It is permissible to interrupt the offset register read sequence with reads or writes to the FIFO. The interruption

is accomplished by deasserting REN, LD, or both together. When REN and LD are restored to a low level,

reading of the offset registers continues where it left off. It should be noted (and care should be taken from the

fact) that when a parallel read of the flag offsets is performed, the data word that was present on output lines

Qn is overwritten.

Parallel reading of the offset registers always is permitted, regardless of which timing mode (Standard or FWFT

modes) has been selected.

retransmit operation

The retransmit operation allows data that has been read to be accessed again. There are two modes of

retransmit operation: normal latency and zero latency. There are two stages to retransmit. The first stage is a

setup procedure that resets the read pointer to the first location of memory. The second stage is the actual

retransmit, which consists of reading out the memory contents, starting at the beginning of memory.

Retransmit setup is initiated by holding RT low during a rising RCLK edge. REN and WEN must be high before

bringing RT low. When zero latency is utilized, REN need not be high before bringing RT low. At least two words,

but no more than D – 2 words should have been written into the FIFO, and read from the FIFO, between reset

(master or partial) and the time of retransmit setup, D = 1024 for the SN74V3640, D = 2048 for the SN74V3650,

D = 4096 for the SN74V3660, D = 8192 for the SN74V3670, D = 16384 for the SN74V3680, and D = 32768 for

the SN74V3690. In FWFT mode, D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the

SN74V3660, D = 8193 for the SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690.

If standard mode is selected, the FIFO marks the beginning of the retransmit setup by setting EF low. The

change in level is noticeable only if EF was high before setup. During this period, the internal read pointer is

initialized to the first location of the RAM array.

When EF goes high, retransmit setup is complete and read operations can begin, starting with the first location

in memory. Because standard mode is selected, every word read, including the first word following retransmit

setup, requires a low on REN to enable the rising edge of RCLK.

See Figure 11 for timing information.

If FWFT mode is selected, the FIFO marks the beginning of the retransmit setup by setting OR high. During this

period, the internal read pointer is set to the first location of the RAM array.

When OR goes low, retransmit setup is complete. At the same time, the contents of the first location appear on

the outputs. Because FWFT mode is selected, the first word appears on the outputs and no low on REN is

necessary. Reading all subsequent words requires a low on REN to enable the rising edge of RCLK.

See Figure 12 for timing information.

For either standard mode or FWFT mode, updating of PAE, HF, and PAF begins with the rising edge of RCLK

that RT is set up on. PAE is synchronized to RCLK, thus, on the second rising edge of RCLK after RT is set up,

PAE is updated. HF is asynchronous, thus, the rising edge of RCLK that RT is set up on updates HF. PAF is

synchronized to WCLK, thus, the second rising edge of WCLK that occurs tsk after the rising edge of RCLK that

RT is set up on updates PAF. RT is synchronized to RCLK.

The retransmit function has the option of two modes of operation, either normal latency or zero latency.

Figures 11 and 12 show normal latency. Figures 13 and 14 show the zero-latency retransmit operation. Zero

latency means, basically, that the first data word to be retransmitted is placed in the output register, with respect

to the RCLK pulse that initiated the retransmit.

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