SN74V3640 datasheet(30/50 Pages) TI

Part #	SN74V3640

Description	1024 횞 36, 2048 횞 36, 4096 횞 36, 8192 횞 36, 16384 횞 36, 32768 횞 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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30 / 50 page

SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690

1024

× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003

30

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

tDS

tOLZ

No Operation

RCLK

REN

EF

OE

WEN

1

2

No Operation

Last Word

tsk1

(see Note A)

tref

tOLZ

tOHZ

tENH

tENS

tDH

tENH

tENS

tDS

tDH

Last Word

tENS

tENH

tCLKH

tCLKL

tENS

tENH

tA

tref

tA

tref

tA

tOE

WCLK

Q0–Qn

D0–Dn

D0

D1

D0

D1

tCLK

tENS

NOTES: A. tsk1 is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that EF goes high (after one

RCLK cycle + tref). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tsk1, EF deassertion can

be delayed one additional RCLK cycle.

B. LD = high

C. First-data-word latency: tsk1 + 1TRCLK + tREF

Figure 5. Read Cycle, Empty Flag, and First-Data-Word Latency Timing (Standard Mode)

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