SN74V3640 datasheet(29/50 Pages) TI

Part #	SN74V3640

Description	1024 횞 36, 2048 횞 36, 4096 횞 36, 8192 횞 36, 16384 횞 36, 32768 횞 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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29 / 50 page

SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690

1024

× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003

29

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

tCLKH

tENS

tDS

tWFF

Data Read

Next Data Read

Data in Output Register

tENH

tsk1

(see Note A)

tsk1

(see Note A)

tCLKH

WEN

RCLK

REN

WCLK

1

2

1

2

Dx

Dx + 1

FF

tDS

tWFF

tA

Q0–Qn

D0–Dn

tDH

No Write

tCLK

No Write

NOTES: A. tsk1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high (after one

WCLK cycle + tWFF). If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tsk1, FF

deassertion can be delayed one additional WCLK cycle.

B. LD = high, OE = low, EF = high

Figure 4. Write Cycle and Full Flag Timing (Standard Mode)

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SN74V3640 Datasheet(PDF) 29 Page - Texas Instruments

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