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SN74V3640 Datasheet(PDF) 21 Page - Texas Instruments

Part # SN74V3640
Description  102436, 204836, 409636, 819236, 1638436, 32768 횞 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74V3640 Datasheet(HTML) 21 Page - Texas Instruments

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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024
× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
1st Parallel Offset Write/Read Cycle
Data Inputs/Outputs
D/Q35
D/Q15
D/Q8
D/Q0
EMPTY OFFSET REGISTER (PAE) BIT LOCATIONS
X
X
X
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Noninterspersed Parity
X
X
X
X
X
15
14
13
12
11
10
9
X
8
7
6
5
4
3
2
1
Interspersed Parity
2nd Parallel Offset Write/Read Cycle
Data Inputs/Outputs
D/Q35
D/Q17
D/Q8
D/Q0
FULL OFFSET REGISTER (PAF) BIT LOCATIONS
X
X
X
X
X
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Noninterspersed Parity
X
X
X
X
16
15
14
13
12
11
10
9
X
8
7
6
5
4
3
2
1
Interspersed Parity
×36 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q17
D/Q15
Data Inputs/Outputs
D/Q0
EMPTY OFFSET (LSB) REGISTER (PAE) BIT LOCATIONS
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Noninterspersed Parity
X
15
14
13
12
11
10
9
X
8
7
6
5
4
3
2
1
Interspersed Parity
D/Q8
2nd Parallel Offset Write/Read Cycle
D/Q17
D/Q15
Data Inputs/Outputs
D/Q0
FULL OFFSET (LSB) REGISTER (PAF) BIT LOCATIONS
X
X
X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Noninterspersed Parity
X
15
14
13
12
11
10
9
X
8
7
6
5
4
3
2
1
Interspersed Parity
D/Q8
×18 Bus Width
Number of bits used:
10 bits for the SN74V3640
11 bits for the SN74V3650
12 bits for the SN74V3660
13 bits for the SN74V3670
14 bits for the SN74V3680
15 bits for the SN74V3690
Note: All unused bits of the
LSB and MSB are don’t care.
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
Figure 1Figure 2


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