SN74V3640 datasheet(20/50 Pages) TI

Part #	SN74V3640

Description	1024 횞 36, 2048 횞 36, 4096 횞 36, 8192 횞 36, 16384 횞 36, 32768 횞 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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20 / 50 page

SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690

1024

× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003

20

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 4. Status Flags for FWFT Mode

SN74V3640

SN74V3650

SN74V3660

SN74V3670

IR

PAF

HF

PAE

OR

0

L

H

L

H

Number of

1 to (n + 1)

L

H

L

Number of

Words in

(n + 2) to 513

(n + 2) to 1025

(n + 2) to 2049

(n + 2) to 4097

L

H

L

FIFO (see

Note 8)

514 to

[1025 – (m + 1)]

1026 to

[2049 – (m + 1)]

2050 to

[4097 – (m + 1)]

4098 to

[8193 – (m + 1)]

L

H

L

H

L

(1025 – m) to 1024

(2049 – m) to 2048

(4097 – m) to 4096

(8193 – m) to 8192

L

H

L

1025

2049

4097

8193

H

L

H

L

SN74V3680

SN74V3690

IR

PAF

HF

PAE

OR

0

L

H

L

H

Number of

1 to (n + 1)

L

H

L

Number of

Words in

(n + 2) to 8193

(n + 2) to 16385

L

H

L

FIFO (see

Note 8)

8194 to [16385 – (m + 1)]

16386 to

[32769 – (m + 1)]

L

H

L

H

L

(16385 – m) to 16384

(32769 – m) to 32768

L

H

L

16385

32769

H

L

H

L

NOTE 8: See Table 2 for values for n, m.

LD

WEN

REN

SEN

WCLK

RCLK

SN74V3640, SN74V3650, SN74V3660,

SN74V3670, SN74V3680, SN74V3690

0

1

↑

X

Parallel write to registers:

Empty offset (LSB)

Empty offset (MSB)

Full offset (LSB)

Full offset (MSB)

0

1

0

1

X

↑

Parallel read from registers:

Empty offset (LSB)

Empty offset (MSB)

Full offset (LSB)

Full offset (MSB)

0

1

0

↑

X

Serial shift into registers:

20 bits for the SN74V3640

22 bits for the SN74V3650

24 bits for the SN74V3660

26 bits for the SN74V3670

28 bits for the SN74V3680

30 bits for the SN74V3690

1 bit for each rising WCLK edge,

starting with empty offset (LSB)

ending with full offset (MSB)

X

1

X

No operation

1

0

X

↑

X

Write memory

1

X

0

X

↑

Read memory

1

X

No operation

NOTES: A. The programming method can be selected only at master reset.

B. Parallel reading of the offset registers is always permitted, regardless of which programming method has been selected.

C. The programming sequence applies to FWFT and standard modes.

Figure 3. Programmable Flag Offset Programming Sequence

Figure 1Figure 2

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