SN74V3640 datasheet(2/50 Pages) TI

Part #	SN74V3640

Description	1024 횞 36, 2048 횞 36, 4096 횞 36, 8192 횞 36, 16384 횞 36, 32768 횞 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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2 / 50 page

SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690

1024

× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003

2

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

WEN

SEN

DNC

VCC

DNC

IW

D35

D34

D33

D32

VCC

D31

D30

GND

D29

D28

D27

D26

D25

D24

D23

GND

D22

VCC

D21

D20

D19

D18

GND

D17

D16

D15

D14

D13

VCC

D12

GND

D11

OE

VCC

Q35

Q34

Q33

Q32

GND

Q31

Q30

Q29

Q28

Q27

Q26

VCC

Q25

Q24

GND

Q23

Q22

Q21

Q20

Q19

Q18

GND

Q17

Q16

VCC

Q15

Q14

Q13

Q12

GND

Q11

Q10

PEU PACKAGE

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DNC = Do not connect

description (continued)

The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO

on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and

read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted.

An output-enable (OE) input is provided for 3-state control of the outputs.

Similar Part No. - SN74V3640

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SN74V3640 Datasheet(PDF) 2 Page - Texas Instruments

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