SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690

1024

× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003

14

POST OFFICE BOX 655303

–0.5 V to 4.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–55

°C to 125°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

TYP

MAX

UNIT

VCC

Supply voltage (see Note 1)

3.15

3.3

3.45

V

GND

Supply voltage

0

0

0

V

VIH

High-level input voltage (see Note 2)

2

5.5

V

VIL

Low-level input voltage (see Note 3)

0.8

V

TA

Operating free-air temperature

0

70

°C

NOTES:

1. VCC = 3.3 V ± 0.15 V, JEDEC JESD8-A compliant

2. Outputs are not 5-V tolerant.

3. 1.5-V undershoots are allowed for 10 ns once per cycle.

15 ns (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

IOH = –2 mA

2.4

V

VOL

IOL = 8 mA

0.4

V

II

VI = VCC to 0.4 V

±1

µA

IOZ

OE

≥ VIH,

VO = VCC to 0.4 V

±10

µA

ICC1

See Notes 4, 5, and 6

40

mA

ICC2

See Notes 4 and 7

15

mA

CIN

VI = 0,

TA = 25°C,

f = 1 MHz

10

pF

COUT

VO = 0,

TA = 25°C,

f = 1 MHz,

Output deselected (OE

≥ VIH)

10

pF

NOTES:

4. Tested with outputs open (IOUT = 0)

5. RCLK and WCLK switch at 20 MHz and data inputs switch at 10 MHz.

6. Typical ICC1 = 4.2 + 1.4 × fS + 0.02 × CL × fS (in mA), with VCC = 3.3 V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz,

using TTL levels), data switching at fS/2, CL = capacitive load (in pF)

7. All inputs = (VCC – 0.2 V) or (GND + 0.2 V), except RCLK and WCLK, TA = 25°C, which switch at 20 MHz.