SN74V3640 datasheet(13/50 Pages) TI

Part #	SN74V3640

Description	1024 횞 36, 2048 횞 36, 4096 횞 36, 8192 횞 36, 16384 횞 36, 32768 횞 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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Manufacturer	TI [Texas Instruments]

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13 / 50 page

SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690

1024

× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003

13

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

half-full flag (HF)

HF indicates a half-full FIFO. The rising WCLK edge that fills the FIFO beyond half-full sets HF low. The flag

remains low until the difference between the write and read pointers becomes less than, or equal to, one-half

of the total depth of the device. The rising RCLK edge that accomplishes this condition sets HF high.

In standard mode, if no reads are performed after reset (MRS or PRS), HF goes low after (D/2 + 1) writes to

the FIFO, where D = 1024 for the SN74V3640, D = 2048 for the SN74V3650, D = 4096 for the SN74V3660,

D = 8192 for the SN74V3670, D = 16384 for the SN74V3680, and D = 32768 for the SN74V3690.

In FWFT mode, if no reads are performed after reset (MRS or PRS), HF goes low after [(D – 1)/2] + 2 writes

to the FIFO, where D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the SN74V3660,

D = 8193 for the SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690.

See Figure 22 for timing information. Because HF is updated by both RCLK WCLK, it is considered

asynchronous.

data outputs (Q0-Qn)

Q0–Q35 are data outputs for 36-bit-wide data. Q0–Q17 are data outputs for 18-bit-wide data. Q0–Q8 are data

outputs for 9-bit-wide data.

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