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SN74V3640 Datasheet(PDF) 10 Page - Texas Instruments |
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SN74V3640 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 50 page  SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690 1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 read enable (REN) When REN is low, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle, if the device is not empty. When REN is high, the output register holds the previous data and no new data is loaded into the output register. The data outputs Q0–Qn maintain the previous data value. In standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be requested using REN. When the last word has been read from the FIFO, the empty flag (EF) goes low, inhibiting further read operations. REN is ignored when the FIFO is empty. Once a write is performed, EF goes high, allowing a read to occur. The EF flag is updated by two RCLK cycles + tsk after the valid WCLK cycle. In FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third valid low-to-high transition of RCLK + tsk after the first write. REN need not be asserted low. In order to access all other words, a read must be executed using REN. The RCLK low-to-high transition after the last word has been read from the FIFO and OR goes high with a true read (RCLK with REN = low), inhibiting further read operations. REN is ignored when the FIFO is empty. serial enable (SEN) The SEN input is an enable used only for serial programming of the offset registers. The serial programming method must be selected during master reset. SEN always is used with LD. When these lines are both low, data at the SI input can be loaded into the program register, with one bit for each low-to-high transition of WCLK. When SEN is high, the programmable registers retain the previous settings and no offsets are loaded. SEN functions the same way in standard and FWFT modes. output enable (OE) When output enable is asserted (low), the parallel output buffers receive data from the output register. When OE is high, the output data bus (Qn) goes into the high-impedance state. load (LD) LD is a dual-purpose pin. During master reset, the state of the LD input, along with FSEL0 and FSEL1, determines one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can be programmed, parallel or serial (see Table 2). After master reset, LD enables write operations to, and read operations from, the offset registers. Only the offset loading method currently selected can be used to write to the registers. Offset registers can be read only in parallel. After master reset, LD activates the programming process of the flag offset values PAE and PAF. Pulling LD low begins a serial loading, or a parallel load, or a read of these offset values. bus matching (BM, IW, OW) BM, IW, and OW define the input and output bus widths. During master reset, the state of these pins is used to configure the device bus sizes (see Table 1 for control settings). All flags operate on the word/byte-size boundary, as defined by the selection of bus width (see Figure 4 for the bus-matching byte arrangement). big endian/little endian (BE) During master reset, a low on BE selects big-endian operation. A high on BE during master reset selects little-endian format. This function is useful when the following input-to-output bus widths are implemented: ×36 to ×18, ×36 to ×9, ×18 to ×36, and ×9 to ×36. If big-endian mode is selected, the MSB (word) of the long word written into the FIFO is read out of the FIFO first, followed by the LSB. If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The desired mode is configured during master reset by the state of BE (see Figure 4 for bus-matching byte arrangement). |
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