SN74V3640 datasheet(7/50 Pages) TI

Part #	SN74V3640

Description	1024 횞 36, 2048 횞 36, 4096 횞 36, 8192 횞 36, 16384 횞 36, 32768 횞 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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7 / 50 page

SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690

1024

× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003

7

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME

I/O

DESCRIPTION

REN

I

Read enable. REN enables RCLK for reading data from the FIFO memory and offset registers.

RM†

I

Retransmit latency mode. During master reset, a low on RM selects zero-latency retransmit timing mode. A high on

RM selects normal-latency mode.

RT

I

Retransmit. RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to low (OR

to high in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode, or

programmable-flag settings. RT is useful to reread data from the first physical location of the FIFO.

SEN

I

Serial enable. SEN enables serial loading of programmable flag offsets.

WCLK

I

Write clock. When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the

programmable registers for parallel programming and, when enabled by SEN, the rising edge of WCLK writes one bit

of data into the programmable register for serial programming.

WEN

I

Write enable. WEN enables WCLK for writing data into the FIFO memory and offset registers.

† Inputs should not change state after master reset.

detailed description

inputs

data in (D0–Dn)

D0–D35 are data inputs for 36-bit-wide data. D0–D17 are data inputs for 18-bit-wide data. D0–D8 are data

inputs for 9-bit-wide data.

controls

master reset (MRS)

A master reset is accomplished when MRS is taken low. This operation sets the internal read and write pointers

to the first location of the RAM array. PAE goes low, PAF goes high, and HF goes high.

If FWFT/SI is low during master reset, the standard mode, EF, and FF are selected. EF goes low and FF goes

high. If FWFT/SI is high, the FWFT mode, IR, and OR are selected. OR goes high and IR goes low.

All control settings, such as OW, IW, BM, BE, RM, PFM, and IP are defined during the master reset cycle.

During a master reset, the output register is initialized to all zeroes. A master reset is required after power up,

before a write operation can take place. MRS is asynchronous.

See Figure 5 for timing information.

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