SN74V3640 datasheet(5/50 Pages) TI

Part #	SN74V3640

Description	1024 횞 36, 2048 횞 36, 4096 횞 36, 8192 횞 36, 16384 횞 36, 32768 횞 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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Manufacturer	TI [Texas Instruments]

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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690

1024

× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003

5

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

description (continued)

If the asynchronous PAE/PAF configuration is selected, PAE is asserted low on the low-to-high transition of

RCLK. PAE is reset to high on the low-to-high transition of WCLK. Similarly, PAF is asserted low on the

low-to-high transition of WCLK, and PAF is reset to high on the low-to-high transition of RCLK.

If the synchronous PAE/PAF configuration is selected , the PAE is asserted and updated on the rising edge of

RCLK only, and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only, and not

RCLK. The mode desired is configured during master reset by the state of the programmable flag mode (PFM).

The retransmit function allows data to be reread from the FIFO more than once. A low on the retransmit (RT)

input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location

of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode

(RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset

selects normal latency.

If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output

register, with respect to the same RCLK edge that initiated the retransmit, if RT is low.

See Figures 11 and 12 for normal latency retransmit timing. See Figures 13 and 14 for zero-latency retransmit

timing.

The devices can be configured with different input and output bus widths (see Table 1).

Table 1. Bus-Matching Configuration Modes†

BM

IW

OW

WRITE-PORT

WIDTH

READ-PORT

WIDTH

L

×36

H

L

×36

×18

H

L

H

×36

×9

H

L

×18

×36

H

×9

×36

† Logic levels during master reset

A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO

in long-word (

×36/×18) format and read out of the FIFO in small-word (×18/×9) format. If big-endian mode is

selected, the most-significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO

first, followed by the least-significant byte (LSB). If little-endian format is selected, the LSB of the long word

written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset

by the state of the big-endian/little-endian (BE) pin (see Figure 4 for the bus-matching byte arrangement).

The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded

into the parallel port (D0–Dn) when programming the flag offsets. If interspersed-parity mode is selected, the

FIFO assumes that the parity bit is located in bit positions D8, D17, D26, and D35 during the parallel

programming of the flag offsets. If noninterspersed-parity mode is selected, D8, D17, and D26 are assumed

to be valid bits, and D32, D33, D34, and D35 are ignored. Interspersed parity mode is selected during master

reset by the state of the IP input. Interspersed parity control has an effect only during parallel programming of

the offset registers. It does not affect data written to and read from the FIFO.

The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are fabricated using

high-speed submicron CMOS technology, and are characterized for operation from 0

°C to 70°C.

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