SN74V3640 datasheet(44/50 Pages) TI

Part #	SN74V3640

Description	1024 횞 36, 2048 횞 36, 4096 횞 36, 8192 횞 36, 16384 횞 36, 32768 횞 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690

1024

× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003

44

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

operating configurations

width-expansion configuration

Word width can be increased by connecting the control signals of multiple devices together. Status flags can

be detected from any one device. The exceptions are the EF and FF functions in standard mode and the IR and

OR functions in FWFT mode. Because of variations in skew between RCLK and WCLK, it is possible for EF/FF

deassertion and IR/OR assertion to vary by one cycle between FIFOs. In standard mode, such problems can

be avoided by creating composite flags, that is, ANDing EF of every FIFO and separately ANDing FF of every

FIFO. In FWFT mode, composite flags can be created by ORing OR of every FIFO and separately ORing IR

of every FIFO.

Figure 23 demonstrates a width expansion using two SN74V3640, SN74V3650, SN74V3660, SN74V3670,

SN74V3680, and SN74V3690 devices. D0–D35 from each device form a 72-bit-wide input bus and Q0–Q35

from each device form a 72-bit-wide output bus. Any word width can be attained by adding additional

SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 devices.

(Qm + 1) – Qn

Read Clock (RCLK)

Read Enable (REN)

Output Enable (OE)

Write Clock (WCLK)

Retransmit (RT)

Half-Full Flag (HF)

Write Enable (WEN)

Load (LD)

First-Word Fall-Through/Serial Input

(FWFT/SI)

Programmable

Almost-Full Flag (PAF)

Data In

Partial Reset (PRS)

Master Reset (MRS)

m + n

Full Flag/Input Ready 2

(FF/IR)

Full Flag/Input Ready 1

(FF/IR)

Empty Flag/Output Ready 2

(EF/OR)

D0–Dm

m

(Dm + 1) – Dn

n

Q0–Qm

m

n

m + n

Data Out

SN74V3640

SN74V3650

SN74V3660

SN74V3670

SN74V3680

SN74V3690

SN74V3640

SN74V3650

SN74V3660

SN74V3670

SN74V3680

SN74V3690

Programmable

Almost-Empty Flag (PAE)

Empty Flag/Output Ready 1

(EF/OR)

Gate

NOTES: A. Use an OR gate in FWFT mode and an AND gate in standard mode.

B. Do not connect any output control signals together directly.

C. FIFO 1 and FIFO 2 must be the same depth, but can be different word widths.

(see Note A)

FIFO 1

FIFO 2

Figure 20. 1024

× 72, 2048 × 72, 4096 × 72, 8192 × 72, 16384 × 72, 32768 × 72

Width-Expansion Block Diagram

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