SN74V3640 datasheet(41/50 Pages) TI

Part #	SN74V3640

Description	1024 횞 36, 2048 횞 36, 4096 횞 36, 8192 횞 36, 16384 횞 36, 32768 횞 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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Manufacturer	TI [Texas Instruments]

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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690

1024

× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003

41

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D – (m + 1) Words in FIFO

D – m Words in FIFO

WCLK

WEN

PAF

RCLK

REN

tCLKH

tENS

tENH

tPAFA

tENS

D – (m + 1) Words in FIFO

tCLKL

NOTES: A. m = PAF offset

B. D = maximum FIFO depth

In FWFT mode: D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the SN74V3660, D = 8193 for the

SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690.

In standard mode: D = 1024 for the SN74V3640, D = 2048 for the SN74V3650, D = 4096 for the SN74V3660, D = 8192 for the

SN74V3670, D = 16384 for the SN74V3680, and D = 32768 for the SN74V3690.

C. PAF is asserted to low on WCLK transition and reset to high on RCLK transition.

D. Select this mode by setting PFM low during master reset.

Figure 17. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Modes)

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