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SN74V3640 Datasheet(PDF) 40 Page - Texas Instruments |
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SN74V3640 Datasheet(HTML) 40 Page - Texas Instruments |
40 / 50 page ![]() SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690 1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tCLKL tENH n Words in FIFO (see Note B) n + 1 Words in FIFO (see Note C) tsk2 (see Note D) WCLK WEN RCLK 12 1 2 REN tENS tPAES n Words in FIFO (see Note B) n + 1 Words in FIFO (see Note C) tPAES tENS tENH n Words in FIFO (see Note B) n + 1 Words in FIFO (see Note C) NOTES: A. n = PAE offset B. For standard mode C. For FWFT mode D. tsk2 is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that PAE goes high (after one RCLK cycle + tPAES). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tsk2, PAE deassertion can be delayed one additional RCLK cycle. E. PAE is asserted and updated on the rising edge of WCLK only. F. Select this mode by setting PFM high during master reset. PAE tCLKH Figure 16. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Modes) |
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