SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690

1024

× 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003

35

POST OFFICE BOX 655303

WCLK

RCLK

REN

RT

PAF

HF

PAE

12

1

2

WEN

3

tENS

tENH

tA

tA

tA

tA

tA

tsk2

tRTS

tENS

tENH

tHF

tPAES

Q0–Qn

Wx

Wx + 1

W0

W3

EF

(see Note A)

tPAFS

W1 (see Note C)

W2 (see Note C)

NOTES: A. If the FIFO is empty at the point of retransmit, EF is updated, based on RCLK (retransmit clock cycle). Valid data appears on the

output.

B. OE = low, enables data to be read on outputs Q0–Qn

C. W1 = first word written to the FIFO after master reset, W2 = second word written to the FIFO after master reset

D. No more than (D – 2) words may be written to the FIFO between reset (master or partial) and retransmit setup. Therefore, FF is

high throughout the retransmit setup procedure.

D = 1024 for the SN74V3640, D = 2048 for the SN74V3650, D = 4096 for the SN74V3660, D = 8192 for the SN74V3670,

D = 16384 for the SN74V3680, D = 32768 for the SN74V3690.

E. At least two words must be written to and read from the FIFO before a retransmit operation can be invoked.

F. RM is set low during MRS.

Figure 10. Zero-Latency Retransmit Timing (Standard Mode)