×

×

×

×

×

×

tOE

WCLK

WD

tENH

tENS

WEN

tsk1

(see Note A)

12

tDH

tDS

D0–D17

RCLK

tENS

tENS

REN

OE

tOHZ

tA

tA

tA

tA

tA

tA

tREF

Q0–Q17

tPAES

tHF

tPAFS

tWFF

tWFF

OR

PAE

HF

PAF

IR

W1

W1

W2

W3

W(m+3)

Wm+2

W(m+4)

WW

W(D-n-1)

W(D-n)

W(D-n+2)

W(D-1)

WD

NOTES: A. tsk1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that IR goes low after one WCLK cycle + tWFF. If the time between the rising

edge of RLCK and the rising edge of WCLK is less than tsk1, IR assertion may be delayed an additional WCLK cycle.

B. tsk2 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that PAF to goes high after one WCLK cycle + tPAFS. If the time between the

rising edge of RCLK and the rising edge of WCLK is less than tsk2, PAF deassertion may be delayed an additional WCLK cycle.

C. LD = high

D. n = PAE offset, m = PAF offset, D = maximum FIFO depth

E. D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 8193 for the SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690

tsk2

(see Note B)

2

1

W(D-n+1)

D–1

2

) 1

D–1

2

) 2

Figure 7. Read Timing (FWFT Mode)