SN54ALS86, SN54AS86A, SN74ALS86, SN74AS86A

QUADRUPLE 2INPUT EXCLUSIVEOR GATES

SDAS006B − APRIL 1982 − REVISED DECEMBER 1994

Copyright

1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

description

These devices contain four independent 2-input

exclusive-OR gates. They perform the Boolean

functions Y = A

⊕ B or Y = AB + AB in positive

logic.

A common application is as a true/complement

element. If one of the inputs is low, the other input

is reproduced in true form at the output. If one of

the inputs is high, the signal on the other input is

reproduced inverted at the output.

The

SN54ALS86

and

SN54AS86A

are

characterized for operation over the full military

temperature range of − 55

°C to 125°C. The

SN74ALS86 and SN74AS86A are characterized

for operation from 0

°C to 70°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

OUTPUT

Y

L

L

L

L

HH

H

LH

H

H

L

1

1A

2

1B

4

2A

5

2B

9

3A

10

3B

12

4A

13

4B

1Y

3

2Y

6

3Y

8

4Y

11

= 1

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

SN54ALS86, SN54AS86A ...J PACKAGE

SN74ALS86, SN74AS86A ...D OR N PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

4B

4A

4Y

3B

3A

3Y

SN54ALS86, SN54AS86A . . . FK PACKAGE

(TOP VIEW)

32

1 20 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

4A

NC

4Y

NC

3B

1Y

NC

2A

NC

2B

NC − No internal connection

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.