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LIS202DL Datasheet(PDF) 27 Page - STMicroelectronics |
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LIS202DL Datasheet(HTML) 27 Page - STMicroelectronics |
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27 / 36 page  LIS202DL Register description 27/36 Wake-up source register. Read only register. Reading at this address clears WU_SRC_2 register and the WU_2 interrupt and allows the refreshment of data in the WU_SRC_2 register if the latched option was chosen. 7.15 WU_THS_2 (36h) Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is reset when the interrupt is no more active else if DCRM=1 duration counter is decremented. 7.16 WU_DURATION_2 (37h) Duration register for Wake-Up interrupt 2. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified. XH X High. Default value: 0 (0: no interrupt; 1: XH event has occurred) XL X Low. Default value: 0 (0: no interrupt; 1: XL event has occurred) Table 33. Register description Table 34. Register DCRM THS6 THS5 THS4 THS3 THS2 THS1 THS0 Table 35. Register description DCRM Resetting mode selection. Default value: 0 (0: counter reset; 1: counter decrements) THS6, THS0 Wake-up Threshold. Default value: 000 0000 Table 36. Register D7 D6 D5 D4 D3 D2 D1 D0 Table 37. Register description D7-D0 Duration value. Default value: 0000 0000 |
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