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LIS202DL Datasheet(PDF) 14 Page - STMicroelectronics |
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LIS202DL Datasheet(HTML) 14 Page - STMicroelectronics |
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14 / 36 page  Digital interfaces LIS202DL 14/36 Transfer when Master is writing one byte to slave: Transfer when Master is writing multiple bytes to slave: Transfer when Master is receiving (reading) one byte of data from slave: Transfer when Master is receiving (reading) multiple bytes of data from slave: Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to read. In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge. 5.2 SPI bus interface The LIS202DL SPI is a bus slave. The SPI allows to write and read the registers of the device. The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Master ST SAD + W SUB DATA SP Slave SAK SAK SAK Master ST SAD + W SUB DATA DATA SP Slave SAK SAK SAK SAK Master ST SAD+W SUB SR SAD+R NMAK SP Slave SAK SAK SAK DATA Master ST SAD + W SUB SR SAD + R MAK Slave SAK SAK SAK DATA Master MAK NMAK SP Slave DATA DATA |
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