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W83977EF-AW Datasheet(PDF) 21 Page - Winbond |
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W83977EF-AW Datasheet(HTML) 21 Page - Winbond |
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21 / 142 page  W83977EF-AW/W83977EG-AW Publication Release Date: Apr. 2006 -19- Revision 1.2 5. FDC FUNCTIONAL DESCRIPTION 5.1 W83977EF/EG FDC The floppy disk controller of W83977EF/EG integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports up to 2 M bits/sec data rate. The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital Data Separator, FIFO, and FDC Core. 5.1.1 AT interface The interface consists of the standard asynchronous signals:RD#, WR#, A0-A3, IRQ, DMA control, and a data bus. The address lines select between the configuration registers, the FIFO and control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal modes. The PS/2 register sets are a superset of the registers found in a PC/AT. 5.1.2 FIFO (Data) The FIFO is 16 bytes in size and has programmable threshold values. All command parameter information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the CONFIGURE command. The advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following tables give several examples of the delays with a FIFO. The data are based upon the following formula: THRESHOLD # × (1/DATA/RATE) *8 - 1.5 μS = DELAY FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 500K BPS Data Rate 1 Byte 1 × 16 μS - 1.5 μS = 14.5 μS 2 Byte 2 × 16 μS - 1.5 μS = 30.5 μS 8 Byte 8 × 16 μS - 1.5 μS = 6.5 μS 15 Byte 15 × 16 μS - 1.5 μS = 238.5 μS FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 1M BPS Data Rate 1 Byte 1 × 8 μS - 1.5 μS = 6.5 μS 2 Byte 2 × 8 μS - 1.5 μS = 14.5 μS 8 Byte 8 × 8 μS - 1.5 μS = 62.5 μS 15 Byte 15 × 8 μS - 1.5 μS = 118.5 μS |
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