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W83977EF-AW Datasheet(PDF) 87 Page - Winbond |
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W83977EF-AW Datasheet(HTML) 87 Page - Winbond |
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87 / 142 page  W83977EF-AW/W83977EG-AW Publication Release Date: Apr. 2006 -85- Revision 1.2 CR24 (Default 0b1s000s0s) Bit 7: EN16SA = 0 12 bit Address Qualification = 1 16 bit Address Qualification Bit 6: EN48 = 0 The clock input on Pin 1 should be 24 Mhz. = 1 The clock input on Pin 1 should be 48 Mhz. The corresponding power-on setting pin is SOUTB (pin 53). Bit 5 - 3: Reserved. Bit 2: ENKBC = 0 KBC is disabled after hardware reset. = 1 KBC is enabled after hardware reset. This bit is read only, and set/reset by power-on setting pin. The corresponding power-on setting pin is SOUTA (pin 46). Bit 1: Reserved Bit 0: PNPCSV# = 0 The Compatible PnP address select registers have default values. = 1 The Compatible PnP address select registers have no default value. When trying to make a change to this bit, new value of PNPCSV# must be complementary to the old one to make an effective change. For example, the user must set PNPCSV# to 0 first and then reset it to 1 to reset these PnP registers if the present value of PNPCSV# is 1. The corresponding power-on setting pin is NDTRA (pin 44). CR25 (Default 0x00) Bit 7 - 6: Reserved Bit 5: URBTRI Bit 4: URATRI Bit 3: PRTTRI Bit 2 - 1 : Reserved Bit 0: FDCTRI. |
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