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W83977EF-AW Datasheet(PDF) 70 Page - Winbond |
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W83977EF-AW Datasheet(HTML) 70 Page - Winbond |
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70 / 142 page  W83977EF-AW/W83977EG-AW -68- 8. KEYBOARD CONTROLLER The KBC (8042 with licensed KB BIOS) circuit of W83977EF/EG is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM®- compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. Then, the controller will assert an interrupt to the system when data are placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data transmissions. No transmission should be sent to the keyboard or PS/2 mouse until an acknowledge is received for the previous data byte. 8042 P24 P25 P21 P20 P27 P10 P26 T0 P23 T1 P22 P11 KIRQ MIRQ GATEA20 KBRST P17 KINH GP I/O PINS P12~P16 KDAT KCLK MCLK MDAT Multiplex I/O PINS Keyboard and Mouse Interface 8.1 Output Buffer The output buffer is an 8-bit read-only register at I/O address 60H (Default, PnP programmable I/O address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. The output buffer can only be read when the output buffer full bit in the register is "1". 8.2 Input Buffer The input buffer is an 8-bit write-only register at I/O address 60H or 64H (Default, PnP programmable I/O address LD5-CR60, LD5-CR61, LD5-CR62, and LD5-CR63). Writing to address 60H sets a flag to indicate a data write; writing to address 64H sets a flag to indicate a command write. Data written to I/O address 60H is sent to keyboard (unless the keyboard controller is expecting a data byte) through the controller's input buffer only if the input buffer full bit in the status register is “0”. |
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